1. Field of the Invention
This invention relates to a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, and in particular to a technique for providing resistance to skew in a semiconductor memory device in spite of skew in the address transferred from an external device.
2. Description of Related Art
Typical examples of a semiconductor memory device include a DRAM and a SRAM. As is well known, the DRAM is more affordable in price and has a larger capacity than the SRAM, but requires a refreshing operation. The SRAM does not require any refreshing operation and is easily handled, but is more expensive and has a smaller capacity than the DRAM.
A virtual static RAM (called VSRAM) is a known semiconductor memory device having the advantages of the DRAM and the SRAM. The virtual SRAM (sometimes also called PSRAM, Pseudo Static RAM) has a memory cell array of dynamic memory cells like the DRAM, and includes a refresh controller to perform the internal refreshing operation.
One example of a virtual SRAM is disclosed in JP2002-74945A.
In the cycle where access is executed in the virtual SRAM, the word lines specified by the address are activated or inactivated in each cycle. The time period for the word line to be activated (hereinafter referred as ‘activation time’) requires a specific time period. If the cycle time period for the access executed with a single address is shorter than that specific time period, the word line remains inactivated when the word line has not yet been activated sufficiently. Consequently, the data in the memory cell which may be specified by the word lines activated insufficiently may be deleted or rewritten into different data. Hereinafter, the situation in which the data in the memory cell is deleted or rewritten into different data is called ‘data destruction.’ The time period, from the time when the inactivation of the activated word line is started to the time when the activation of any word line is started, (hereinafter referred to as ‘pre-charge time’) requires the specific time period. In the case where the pre-charge time is insufficient, the data destruction also may occur.
The too short activation time or pre-charge time may occur when skew occurs in the address transferred from the external device. Accordingly, it is preferable that data destruction does not occur in a semiconductor memory device even when skew in the address occurs, i.e., the device is resistant to skew.
The present invention is made to address the above mentioned problem, and to provide techniques which achieve resistance to skew that may occur in the address transferred from the external device to the semiconductor memory device, equipped with a memory cell array in which dynamic memory cells, e.g., a virtual SRAM, are arrayed in a matrix.